1. Field of the Invention
The present invention relates to a method and a system for generating a test pattern of an LSI tester, and more specifically to a method and a system for generating an LSI tester pattern used when a final test of a semiconductor integrated circuit is executed by an LSI tester.
2. Description of Related Art
In a fabricating process of the semiconductor integrated circuit, first, a logic circuit is designed in accordance with a required specification of a product, a test pattern is prepared for the logic circuit, and a logic simulation is executed using the test pattern prepared, in order to verify the function and the operation timing of the logic circuit.
Furthermore, before an actually fabricated semiconductor integrated circuit is shipped as a product, a final test of the actually fabricated semiconductor integrated circuit is executed by use of an LSI tester by using the same pattern as the test pattern used in the simulation. In the LSI tester, an output signal outputted from the semiconductor integrated circuit is compared with an expected output value verified in the simulation when the same test pattern is applied. Thus, it is verified that the semiconductor integrated circuit has the same function as that of the designed logic circuit and operates at the same timing as that of the designed logic circuit.
However, there are cases in which when the final test was performed by the LSI tester, the output signal of a non-defective semiconductor integrated circuit is not consistent with the expected output value corresponding to the test pattern, with the result that the non-defective semiconductor integrated circuit is deemed as being a defective. One of causes for this problem is considered to be a tester skew which is a timing difference between signals supplied from pins of the LSI tester to input terminals of the semiconductor integrated circuit.
The LSI tester operates to supply a test pattern to the semiconductor integrated circuit at a designated output timing, namely, at the same timing as that in the simulation. Actually, however, because of an insufficient precision of the LSI tester and a delay of a signal on a tester board, the timing of signals supplied from the LSI tester to the semiconductor integrated circuit, has a skew on the order of several 100 picoseconds to several nanoseconds. Therefore, even if it is intended to supply signals to input terminals of the semiconductor integrated circuit at the same timing, these signals are not necessarily simultaneously inputted to the semiconductor integrated circuit, so that a variation of the input timing occurs within the range of the skew width.
Now, this problem will be further described with reference to FIG. 1, which is a logic diagram illustrating a part of a logic circuit in the semiconductor integrated circuit. The shown partial logic circuit includes external terminals 1, 2 and 3, combinational circuits 5A, 5B, 5C and 5D and flipflops (F/F) 6A and 6B which are sequential unitary circuits. A data signal is supplied from the external terminal 1 through the combinational circuit 5A to a data input D of a second stage flipflop 6B. Another data signal is supplied from the external terminal 2 through the combinational circuit 5B to a data input D of a first stage flipflop 6A. A clock signal is supplied from the external terminal 3 through the combinational circuit 5C to a clock input C of the first stage flipflop 6A.
A data signal is supplied from a data output Q of the first stage flipflop 6A through the combinational circuit 5D to a clock input C of the second stage flipflop 6B.
In order for the flipflop to normally operate, the data signal must become definite a setup time or more before the changing timing of the clock signal, and must be held for a time which starts from the changing timing of the clock signal and which is not shorter than a hold time. If the clock signal and the data signal fulfills this relation, the operation of the flipflop is stable. However, if this relation is not fulfilled, the output of the flipflop is not settled either at a high level or a low level. This condition is called that the clock signal and the data signal xe2x80x9ccontendxe2x80x9d with each other. Therefore, the input timing of the clock signal and the input timing of the data signal must be made to fulfill the above mentioned relation.
In the simulation, if the above relation is fulfilled, an expected value error does not occur in an external output of the semiconductor integrated circuit. However, when the semiconductor integrated circuit is actually tested by the LSI tester, it is in some cases that the above relation is not fulfilled because of the tester skew so that the output of the flipflop does not become definite, and it is in an extreme case that the value should be rightfully latched after the data signal has changed but the value is actually latched before the data signal changes, or alternatively, the value should be rightfully latched before the data signal changes but the value is actually latched after the data signal has changed, with the result that the output value of the flipflop is inverted. If this condition is propagated to the external of the LSI, the non-defective product is discriminated as being defective.
In order to avoid this problem in the prior art, a timing-shifted pattern is prepared by shifting the timing of the pattern change on the input terminals on the basis of the test pattern used in the LSI tester while considering the tester skew, and a logic simulation is executed by using the timing-shifted pattern thus prepared, so as to verify possibility that a trouble in measurement occurs due to the tester skew.
Now, his prior art method will be described with reference to FIG. 2, which is a flow chart illustrating the steps of the prior art method for discriminating the test pattern in order to avoid the trouble in measurement due to the tester skew.
First, a plurality of external terminals concurrently changing the input test patterns (namely, their signal levels) are retrieved from the test pattern for the logic simulation (step S51). The changing timing of the input test patterns (namely, their signal levels) on the external terminals retrieved is shifted from each other, so that a pair of simulation patterns are generated (step S52).
Here, referring to FIGS. 3 and 4, an upper half of these figures shows that the input test patterns (namely, signal levels) on external terminals 1 to 4 concurrently change, and a lower half of these figures shows that, by using the input test pattern on the external terminal 1 as a reference, the changing timing of the input test patterns on the external terminals 2 to 4 are shifted in order by a pattern period T. Specifically, the example of FIG. 3 shows that the changing timing of the input test patterns on the external terminals 2 to 4 are delayed in order from the changing timing of the input test pattern on the external terminal 1. On the other hand, the example of FIG. 4 shows that the changing timing of the input test patterns on the external terminals 2 to 4 are advanced in order from the changing timing of the input test pattern on the external terminal 1.
By using each of the two simulation test patterns 1 and 2 thus prepared, a delayed simulation is executed (step S53 and step S54), and the result of each simulation is examined to check whether or not an error exists in an expected value of output terminals, for the purpose of verifying the skew between the input terminals (step S55). If no error is fount out in each of the two simulations (OK), it is discriminated that there is no possibility that a trouble occurs due to the tester skew, and therefore, the original test pattern can be used in the LSI tester with no modification.
If the expected value error occurs, since there is possibility that a trouble occurs due to the tester skew, it is necessary to modify the test pattern. In this case, however, it is not possible to easily specify which of inter-terminal skews causes the expected value error. Therefore, a massive analysis has to be executed.
The reason for this is that: The prior art method is only to shift the timing of the test patterns in the same way, to execute the simulations and to discriminate OK/NG on the basis of the result of the simulations, but does not have a function of specifying the cause. Therefore, it was not possible to obtain an optimum input timing of the test pattern which has overcome the problem of the inter-terminal skew of the tester.
A prior art for overcoming the prior art problem mentioned above, is disclosed by Japanese Patent Application Pre-examination Publication No. JP-A-09-153073 (an English abstract of which is available and the content of the English abstract is incorporated by reference in its entirety into this application).
Applying this prior art method to two cascaded flipflop stages as shown in FIG. 1, it is recognized that only the first stage flipflop is influenced by the tester skew, and for only the first stage flipflop, the path delay is calculated, and the influence of the tester skew is discriminated.
However, what is influenced by the tester skew is not limited to only the first stage flipflop, and all flipflops causing the contending are influenced by the tester skew. The reason for this will be described with reference to the logic circuit shown in FIG. 1.
When the input test patterns (namely, signal levels) supplied to the external terminal 2 and the external terminals 3 respectively do not change concurrently, no contending occurs in the first stage flipflop 6A. However, if the input test patterns (namely, signal levels) supplied to the external terminal 2 and the external terminals 3 respectively change concurrently, there is possibility that the contending occurs in the second stage flipflop 6B. Therefore, the second stage flipflop 6B is influenced by the tester skew.
Accordingly, it is an object of the present invention to provide a method and a system for generating a test pattern of an LSI tester, which have overcome the above mentioned problem of the prior art.
Another object of the present invention is to provide a method and a system for generating an LSI tester test pattern having a timing relation which causes no contending.
Still another object of the present invention is to provide a method and a system for generating an LSI tester test pattern having a timing relation which causes no contending, by detecting a combination of a sequential unitary circuit such as a flipflop having possibility that a circuit operation changes due to an inter-terminal skew of an LSI tester in view of a circuit construction, with a pair of external input terminals connected to a data input and a clock input of the sequential unitary circuit, by performing a static timing verification for the pair of contending external input terminals so as to obtain a timing relation causing no contending, and by reflecting the thus obtained timing relation to a test program.
A further object of the present invention is to provide a recording medium recording a program for executing the method in accordance with the present invention.
The above and other objects of the present invention are achieved in accordance with the present invention by a method for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having a plurality of external terminals and a plurality of sequential unitary circuits, comprising the steps of:
extracting, from circuit connection information of the semiconductor integrated circuit, at least one first level combination composed of a sequential unitary circuit having a first input and a second input having possibility of causing the contending in a circuit construction, and a pair of potentially contending external terminals connected to the first input and the second input of the sequential unitary circuit;
extracting, from the at least one first level combination thus extracted, at least one second level combination composed of a pair of actually contending external terminals connected to the same sequential unitary circuit and concurrently changing their signal level in a test pattern, and a corresponding sequential unitary circuit;
in each of the at least one second level combination thus extracted, on the basis of a path delay value from each of the actually contending external terminals to the corresponding sequential unitary circuit, and on the basis of the value of a tester skew, determining an optimum timing condition preventing the contending in the sequential unitary circuit; and
generating the test pattern for the LSI tester on the basis of the optimum timing condition thus determined.
According to another aspect of the present invention, there is provided a system for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having a plurality of external terminals and a plurality of sequential unitary circuits, comprising:
a means for extracting, from circuit connection information of the semiconductor integrated circuit, at least one first level combination composed of a sequential unitary circuit having a first input and a second input having possibility of causing the contending in a circuit construction, and a pair of potentially contending external terminals connected to the first input and the second input of the sequential unitary circuit;
a means for extracting, from the at least one first level combination thus extracted, at least one second level combination composed of a pair of actually contending external terminals connected to the same sequential unitary circuit and concurrently changing their signal level in a test pattern, and a corresponding sequential unitary circuit;
a means for determining an optimum timing condition preventing the contending in the sequential unitary circuit, in each of the at least one second level combination thus extracted, on the basis of a path delay value from each of the actually contending external terminals to the corresponding sequential unitary circuit, and on the basis of the value of a tester skew; and
a means for generating the test pattern for the LSI tester on the basis of the optimum timing condition thus determined.
According to still another aspect of the present invention, there is provided a recording medium recording a program for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having a plurality of external terminals and a plurality of sequential unitary circuits, the program comprising the steps of:
extracting, from circuit connection information of the semiconductor integrated circuit, at least one first level combination composed of a sequential unitary circuit having a first input and a second input having possibility of causing the contending in a circuit construction, and a pair of potentially contending external terminals connected to the first input and the second input of the sequential unitary circuit;
extracting, from the at least one first level combination thus extracted, at least one second level combination composed of a pair of actually contending external terminals connected to the same sequential unitary circuit and concurrently changing their signal level in a test pattern, and a corresponding sequential unitary circuit;
in each of the at least one second level combination thus extracted, calculating the path delay value from each of the actually contending external terminals to the corresponding sequential unitary circuit, and obtaining a tester skew margin from the path delay values and a setup time and a hold time of the sequential unitary circuit;
comparing the tester skew margin with the value of a tester skew, to discriminate whether or not at least one of a setup error and a hold error occurs in the sequential unitary circuit when respective input timing of signals to the pair of actually contending external terminals connected to the first input and the second input of the sequential unitary circuit, respectively, are deviated from each other by the value of the tester skew;
when the at least one of a setup error and a hold error occurs, determining an optimum timing condition preventing the contending in the sequential unitary circuit; and
executing a simulation by using the test pattern having the input timing shifted on the basis of the optimum timing condition thus determined, and if the result of the simulation is good, determining the test pattern having the input timing shifted, as the test pattern for the LSI tester.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.